1. Filed of the Invention
The present invention to a semiconductor memory device, and more specifically the present invention relates to a semiconductor memory device so configured as to generate a precharge voltage in the case where a precharge method is used for memory cell reading.
2. Description of the Related Art
For a memory cell reading method in semiconductor memory devices such as MROMs (Mask Read Only Memory), precharge methods have been conventionally proposed. An example will be described below in which a MROM is read by a precharge method. According to the precharge method, a bit line is connected to a memory cell transistor, which is either an ON transistor or an OFF transistor, wherein the bit is first charged to a precharge level for a certain period of time (hereinafter, this time is referred to as a precharge period). After the charging is completed, a sense circuit detects the discharge waveform of the bit line and determines whether the memory cell transistor connected to the bit line is an ON transistor or an OFF transistor.
Memory cell transistors are fabricated by, e.g., an ion injection method, and for making them ON transistors or OFF transistors, for example, the following two methods are used:
In one method, the threshold voltages of transistors are changed so as to form ON transistors which turn to the ON state by applying a voltage VI to their gates and OFF transistors which turn to the OFF state by applying the same voltage V1 to their gates. In the other method, the threshold voltage is not changed. OFF transistors are formed by physically forming an electrical isolation between their sources and drains. For ON transistors, transistors in which the current flows between their sources and drains are used.
FIG. 5 shows a connection example between a precharge circuit and a memory cell transistor in a conventional semiconductor memory device 200. According to the semiconductor memory device 200 in FIG. 5, a precharge circuit includes: a reference voltage generating circuit 30 for generating a reference voltage for charging a bit line 11; and a charge transistor N1 formed of an Nch (N-channel) transistor. An inverter INV1 is used in the reference voltage generating circuit 30. The output of the inverter INV1 is applied to the gate of the charge transistor N1 and the drain of the charge transistor N1 is connected to a supply voltage VCC. The source of the charge transistor N1 is connected to the input terminal of the inverter INV1. The reference voltage generating circuit 30 including the inverter INV1 and a charge transistor N1 together form a feed back bias circuit. The reference voltage generated by the feedback bias circuit is determined by controlling the inversion voltage of the inverter INV1.
The drain of the Nch transistor NTR1 is connected via the bit line 11 to the source of the charge transistor N1. The drain of a memory cell transistor M1 is connected to the source of the Nch transistor NTR1. and the source of the memory cell transistor M1 is connected to the drain of the Nch transistor NTR2. A sense circuit 20 is connected to the bit line 11 between the charge transistor N1 and the Nch transistor NTR1.
The case will now be described where the memory cell transistor M1 of such a semiconductor memory device is an OFF transistor (i.e., no current flows between the source and drain even if the gate voltage is in the H (High) level) and the gate voltages input to the respective gates of the Nch transistor NTR1, the memory cell transistor M1, and the Nch transistor NTR2 are all in the H level. If the bit line 11 connected to the source of the charge transistor N1 is initially in the L (Low) level, the L level is input to the input of the inverter INV1 of the reference voltage generating circuit 30. When the input of the inverter INV1 turns to the L level, the output of the inverter INV1 turns to the H level, and then the H level is input to the gate of the charge transistor N1. The supply voltage VCC, which is connected to the drain of the charge transistor N1, is then applied to the bit line 11.
Since the memory transistor M1 is an OFF transistor, no current path to the GND is provided, and the bit line 11 is charged through the charge transistor N1.
When the bit line 11 is charged to a voltage exceeding the inversion voltage of the inverter INV1, the output of the inverter INV1 turns to the L level and the charge transistor N1 turns to the OFF state. The potential of the bit line 11 then decreases through a spontaneous discharge or the like, and when the potential of the bit line 11 becomes lower than the inversion voltage of the inverter INV1, the output of the inverter INV1 turns again to the H level and the N1 transistor turns to the ON state so as to start the charging of the bit line 11.
By repeating such operations, the bit line 11 is stabilized at a predetermined voltage close to the inversion voltage of the inverter INV1, i.e., the precharge voltage.
In the case where the memory cell transistor M1 is an ON transistor, and the respective gates of the Nch transistor NTR1, memory cell transistor N1, and the Nch transistor NTR2 are all in the H level, the bit line 11 is connected to GND via the Nch transistor NTR1, the memory cell transistor M1, and the Nch transistor NTR2.
When the performance of the charge transistor N1 is low (i.e., the ON resistance is high), the voltage of the bit line 11 can be differentiated between the case where the memory cell transistor M1 is an ON transistor and the case where the memory cell transistor M1 is an OFF transistor. The sense circuit 20 reads the voltage of the bit line 11 and determines whether or not the memory cell transistor M1 is an ON transistor or an OFF transistor.
In recent years, however, the size of memory cells has been significantly reduced and thus the performance (i.e., the current driving performance) of memory cell transistor M1 has declined (i.e., the ON resistance has been higher). This causes the difference of the potentials to become small between of the bit line 11 connected to an ON transistor and the bit line 11 connected to an OFF transistor, and therefore, the sense circuit 20 may not be able to read the difference if the current driving performance of the charge transistor N1 is high. On the other hand, if the performance of the charge transistor N1 is low, the time required to charge the bit line 11 to the precharge voltage is extended, which may prevent a faster reading of the memory cells when the parasitic capacitance of the bit line 11 is large.
In order to solve these problems, a semiconductor memory device 300 shown in FIG. 6 has been proposed. Throughout the drawings, like components are denoted by like reference numerals. The semiconductor memory device 300 has the same configuration as the semiconductor memory device 200 in FIG. 5, except that a high performance (i.e., a low ON resistance) Nch charge transistor N2 is connected to the Nch charge transistor N1 and an Nch transistor NTR0 is connected between the Nch charge transistor N2 and the bit line 11. The gate of the Nch charge transistor N2 is connected to the gate of the Nch charge transistor N1, and the drain of the Nch charge transistor N2 is connected to the supply voltage VCC. The source of the Nch charge transistor N2 is connected to the drain of the Nch transistor NTR0 and the source of the Nch transistor NTR0 is connected to the bit line 11.
The Nch transistor NTR0 is turned ON/OFF by signals generated in a circuit generally known as an ATD circuit (address transition detection circuit). The period while the Nch transistor NTR0 is ON corresponds to the precharge period, during which the bit line 11 is charged.
According to the semiconductor memory device 300, the bit line 11 is charged quickly during the precharge period by the Nch charge transistor N2. When the precharge period ends, the Nch transistor NTR0 turns OFF, and no current flows from the Nch charge transistor N2 to the bit line 11. After the completion of the precharge period, the sense circuit 20 reads the bit line 11 in a manner similar to that of the semiconductor memory device 200 in FIG. 5.
The semiconductor memory device 300 in FIG. 6 can provide a faster reading by the sense circuit 20 because it is possible to make the potential difference large between the ON state and the OFF state of the memory cell transistors of the bit lines 11. Japanese Laid-open Publication No. 3-30193 discloses a similar semiconductor memory device which is capable of a fast reading.
A reference voltage generating circuit 30xe2x80x2 shown in FIG. 7 employs a NOR circuit NOR1 instead of the inverter INV1 of the reference voltage generating circuit 30 of the semiconductor memory device 300 in FIG. 6. One of the two inputs of the NOR circuit NOR1 has a feed back structure similar to that of the inverter INV1 in FIGS. 5 and 6. A switching signal CEB for switching between the stand-by (wait) state and the operation state is applied to the other input of the NOR circuit NOR1.
In this case, when the switching signal CEB is in the L level, the NOR circuit NOR1 functions similar to the inverter INV1 in FIGS. 5 and 6 so as to generate a charge voltage (i.e., the precharge voltage). When the switching signal CEB is in the H level, the NOR circuit NOR1 outputs the L level, causing the reference voltage generating circuit 30xe2x80x2 to be in the stand-by state. Thus, there is no possibility that the voltage of the bit line 11 may increase.
According to the semiconductor memory devices 200 and 300 in FIGS. 5 and 6, and the reference voltage genera ting circuit 30xe2x80x2 in FIGS. 7, a through current flows in the inverter INV1 (FIGS. 5 and 6 ) or the NOR circuit NOR1 (FIG. 7), even if inverter INV1 or the NOR circuit NOR1 is in the CMOS configuration. This is because a predetermined reference voltage is applied to the inverter INV1 or the NOR circuit NOR1 while the inverter INV1 or the NOR circuit NOR1 generates the reference voltage. Therefore, in the case of a high performance MROM where a lot of information is simultaneously read from the memory cells, a plurality of such precharge circuits are required. In such a case, the through current flows in each of the plurality of precharge circuits. This requires a large operation current for the semiconductor memory device.
In order to reduce the operation current in a high performance MROM requiring a plurality of precharge circuits, a reference voltage generating circuit 30xe2x80x3 as shown in FIG. 8 has been proposed, in which a serial circuit including resistors R1 and R2 is used. The output potential of the reference voltage generating circuit 30xe2x80x3 is the same as the potential at the contact point between the resistors R1 and R2. In order to further reduce the operation current of the semiconductor memory device, a similar resistor may be connected to the gate of the Nch charge transistor N1 (FIG. 5), or the gates of the Nch charge transistor N1 and the Nch charge transistor N2 (FIG. 6). Furthermore, one or a few similar resistors may be connected to each of the charge transistors.
According to the device in FIG. 8, by increasing the resistance value of the serial circuit including the resistors R1 and R2, the through current flowing between the supply voltage VCC and GND can be reduced. Furthermore, by connecting one or a few similar resistors to each of the charge transistors, the operation current of the charge transistors as a whole can be reduced.
According to the device in FIG. 8, however, reducing the through current or providing a few resistor-separation circuits extends the time required for charging the gate of the Nch charge transistor N1. Specifically, by reducing the through current, the charge current is also reduced and therefore the time required for charging the gate of the Nch charge transistor N1 is extended. As a result, in the case of an MROM having a stand-by function, the access to the memory cells slows down after the memory device is released from the stand-by state. This may cause the problem that a significant reduction of the through current during the stand-by state is impossible. Therefore, even when the memory device is in the stand-by state, a stand-by current corresponding to the quantity of the through current is present. Accordingly, either in the precharge circuit employing a feedback device or in the precharge circuit employing resistor separation, it is difficult to reduce the stand-by current simultaneously with a reduction of the operation current.
According to one aspect of this invention, there is provided a semiconductor memory device, including: a bit line; a reference voltage generating circuit; a first transistor whose drain or source region is connected to the bit line, a voltage generated in the reference voltage generating circuit being applied to a gate region of the first transistor; and a memory cell connected to the first transistor at least via the bit line, wherein the reference voltage generating circuit includes: a second transistor connected to the first transistor in a source-follower connection; and at least one first element having an electrical resistance for controlling a current flowing the second transistor.
In one embodiment of the invention, the semiconductor memory device further includes: a third transistor whose gate region is connected to the gate region of the fist transistor; a fourth transistor having a source region and a drain region, in which one of the source region or the drain region is connected to either the drain region or the source region of the third transistor, the other of the drain region or the source region of the fourth transistor being connected to the bit line.
In another embodiment of the invention, an ON resistance of the third transistor is lower than an ON resistance of the first transistor.
In still another embodiment of the invention, the second transistor is an Nch transistor.
In still another embodiment of the invention, the at least one first element is a transistor.
In still another embodiment of the invention, the at least one first element is a resistor.
In still another embodiment of the invention, the reference voltage generating circuit further includes: a inversion voltage generating circuit connected to the gate region of the second transistor; and a fifth transistor whose gate region is supplied with an output of the inversion voltage generating circuit, either of the drain and source region of the fifth transistor being connected to the gate region of the first transistor, and the other of the drain and source region being grounded.
Thus, the invention described herein makes possible the advantages of providing a semiconductor memory device having a precharge circuit which is capable of reducing the operation current and the stand-by current at the same time.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.